During this webinar we present in cooperation with GlobalFoundries a complete chip-package co-design flow, which allows improvement of RF performance and power efficiency. By designing concurrently, silicon, package and system can be optimized and validated with fewer iterations before tape-out. The flow has been validated on GlobalFoundries’ 22FDX process which targets mm-Wave designs.
Chip-package co-design flow for mm-Wave applications
Wednesday, November 18, 2020 at 11 a.m. (CET)
The number of mm-Wave applications, in particular within 5G and Automotive Radar, is growing rapidly. While this brings various benefits like extremely low latency and very high bandwidth, it also brings big challenges for the semiconductor industry in designing the RF chips. The level of integration of RF and mm-wave systems is increasing and this has an impact on the electrical properties and system parameters. It is insufficient to model chip, package and PCB separately, as some high-frequency effects may not be captured, as electromagnetic coupling between integrated coils on chip and routing traces in the package. Electromagnetic simulation is used for signal integrity, parasitic extraction and antenna radiation performance. At frequencies around 24, 60 or 77 GHz, EM simulation is a must have and schematic-only simulations becoming meaningless.
Alexander Kravets Application Engineer at Keysight Technologies
Alexander Kravets received his B.Sc. from Technion in Electrical Engineering in 1999, M. Sc. and Ph.D. in High Frequency Engineering from Munich and Berlin Technical Universities in 2005 and 2015, respectively. From 2000 has worked as RF board designer, mmWave IC and RFIC designer for various communications, radar and sensor applications. Has experience in the fields of:microwave/RF IC and board design, system architecture and EM simulation. From 2015 is an application engineer at Keysight Technologies, responsible for RFIC circuit design, EM, electrothermal and system design flows and activities across EMEA.